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Basically all silicon works like this. "Variable cores" actually means some cores are disabled. This is usually done to increase overall yields: chips with damage inside one of the cores can still be binned as the lower core count SKUs.

The "you can scale up" thing is actually just how e.g. Intel makes bigger monolithic chips (Xeon/HEDT) with the same or very similar cores as the desktop ones. Meanwhile AMD, actually using chiplets, can cheaply do something more like "scale out" in the sense that they put more of the exact same die on a package.



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Does anyone know, is the 48-core SKU just a lower-binned version of the 64-core SKU, i.e. where one or more cores on each chiplet have flaws, and so AMD decides to just therefore build parts entirely out of e.g. “7 out of 8 cores enabled” chiplets to create the lower SKUs? (I know the chiplet-oriented manufacturing process makes it cheaper than ever before to get chips right the first time, but that doesn’t mean that they don’t have flawed chiplets sitting around that they could intentionally make use of.)

If so, maybe AMD doesn’t have high-enough yield on their 64-core part (i.e. 8-core chiplet sub-part) to satisfy huge bulk orders for them, without also generating huge numbers of the 48-core-binned SKU (i.e. 6-core chiplets, really 6-out-of-8-enabled-core chiplets) in the process.

And I would suspect that their production process is such that they do have a real, explicit 6-core chiplet part as well, which can be mixed-and-matched within a single CPU with the flawed, re-binned 6-of-8-core chiplets, giving them a powerful hedge on their own logistics (in about the same way that SPAM has flexibility in their ratio of chicken to ham that lets them ride out turbulence in either market, making the end-product cheaper than either input), but requiring even further that people consume the SKUs containing “6”-core chiplets.

I would bet that AMD very much wants to sell large buyers the lower-core-count CPUs, since their yield guarantees that—at least for now—they have so very much more of them, and attempting to make more of the highest-end part ensures that they end up with even more of the less-than-highest-end chiplets laying around.

AMD probably ideally wants order-flow of CPUs in a ratio, e.g. “1x 7742 : 8x 7642”, and offers both better deals monetarily, and far faster delivery (/less contention on orders with other clients) when you take them up on it; or when you buy huge numbers of 7642s alone, such that you’re consuming the cast-off from bullheaded clients who wanted pure 7742s.


The word for CPU manufacturers making multiple SKUs is “binning”. Every processor wafer made could attempts at an 8 core beast, but if 1 isn’t working, they disable another and sell it as a 6 core. If the chip isn’t stable enough for hyperthreading, that feature is disabled. Unstable at high frequencies? The turbo clock is lowered.

Are the manufacturers benevolent in this? Not always. Sometimes an 8 core chip will be locked to 4 just to make more lower end SKU pieces available for purchase. Or Intel disabling overclocking so you have to buy a “K” processor that costs more.

But when people say things like:

> When you buy physical things, you should be paying the total cost for the hardware to be manufactured, distributed, and finally recycled or disposed of.

They’re ignoring the fact that soft limits actually can make manufacture cheaper. The reason Intel/AMD/etc don’t have a separate silicon template for every SKU is it’s too wasteful (money wise). Each run has a setup cost, and if that can be lowered by reusing the same wafer template, they do that. It’s cheaper to have less manufacturing SKUs and just disable features later.

In addition, when soft limits are used on chips, it actually prevents waste. Imagine if the yield on an 8 core wafer was 70%. That means only 70% of the produced chips works at spec. The other 30% would be tossed if binning didn’t happen. By binning, that 30% can be sold (with reduced feature sets).


There is a huge difference.

The number of defects is an average over an area. So if you double your die area then you get double as many defective chips.

Making a bigger chip means you throw away more dies. So Intel's 34 Core would be even more expensive to produce.

Imagine it like taking a low res photo of a paper with dots drawn on it. The bigger the pixel the bigger the black spots on the paper will be. The higher resolution your camera is, ie the smaller the pixel, the more pixels that aren't black, ie defective silicon.

AMD has the advantage here, their 4 core dies are very small so they can produce them with a high yield rate. The defect one with 1 or 2 defect cores but otherwise okay are recycled. Then everything is binned according to their performance (chips can have wildly different performance).

Another advantage Intel does not have. If one core on the 28 core chip does not manage to run stable on 2.8 GHz (example if they sold the chip at that) that means either bin it on the next lower frequency to run at or trash the die.

For AMD a low running chip means getting it into a lower bin. If they build a 32 core CPU with high core they just need to select from 4 core dies that run fast.

The difference here is very surprising, IIRC AMD stated their yield rate is 98%. For comparison, a chip like the 28 core Intel Xeon would be expected to have around 60% if not worse. And Intel can't rebin a bad Xeon for a low power desktop CPU in the lowest market segment since the die is too big for those sockets.


Large core counts are the bread and butter of enterprise/cloud. I suspect Intel is binning those chips for their real customers (not desktop users). Probably has to do with wafer yields or something if I can hazard a guess.

No, binning can't make cores physically smaller which is what AMD is doing.

That's the fairy-tale but most chips come off the line with all cores functional and the manufacturer disables some of the cores. Taken to the extreme - there just aren't that many chips with, say, 4 broken cores and yet the rest of the chip still works. Demand is highest for these cheap parts and supply is lowest, so you disable cores.

The other thing is, these 12Cs are actually clocked significantly higher (and have much more cache enabled) than the lower-end parts. So these are not simply "bad silicon". Really this is a misnomer in general since there is a variety of ways silicon can be "bad". Bad clocks, damaged cache, damaged cores, etc etc.

Binning gives you the opportunity to pick the best cores on a chip too. So if a chip had two cores that could only do 4 GHz but the rest of them could do 4.4 GHz or whatever, then all of them might be functional yet it might fail binning as a fast 8C chip, but you could disable the two derpy cores and ship it as a very fast 6C chip.

The binning process is a deeply trade secret kinda thing, but is undoubtedly much more complex than people generally believe. It's not "top X% silicon becomes Epyc, next X% silicon becomes threadripper", etc. All that is known for sure is that AMD is very efficient at using every part of the buffalo.


Yield might be part of it, but I'm sure intel can ship partially functional chips with a core here/there disabled.

Another of the big advantages for AMD is that their products aren't reticle limited. The basic design lets them have a single design they bolt into dozens of configurations that scale larger than what intel can fit on a single die. Hence 64 "big" cores in a single socket.

There are likely other advantages too (cooling?) that partially make up for the longer more complex core->core latencies.


Right, that's a different strategy again. If you're making a monolithic 64 core die and one of the cores is defective, and the next one down in your product lineup is the 48 core, that's going to make the 64 core model harder to stock (and maybe not worth aiming for at all, if your yields are bad enough that this happens often).

Meanwhile if you're making 6 x 8 core chiplets and one of those cores is defective, well that chiplet can go into a 48 core or be a midrange consumer cpu or something, and you'll just pick one of your many many other 8 core chiplets to go with the rest for the 64 core.


Is this true? I thought most of the reasons why AMD can push higher core counts is largely caused by very recent manufacturing innovations with chiplet/infinity fabric.

Namely that it enabled the manufacturing process to glue together slightly broken CCXes to enable high core count lower binned parts.


Chiplets also drastically improve binning since you no longer need all 16 cores on a monolithic die to run at for example 5ghz, you just need to find 4, 4 core chiplets that run at 5ghz.

It effectively allows you to mix and match parts (to a degree) to make the highest performing cpu.


Interesting, so when they claim it automatically scales out to all cores what they mean is it defaults to 3 unless overridden.

Yep, it’s standard practice. The old AMD tri-core chips for example were all physically four cores with a (usually) broken one disabled. Modern AMD chips use multiple chiplets on a single board to extend yields.

Every chip manufacturer does that, that's how they come up with cheap, low end parts. They just try to keep number of cores an even number, so the trick is less obvious.

Your dual core CPU is often the same quad core die with two of the cores disabled because one of the cores has a defect and is sold at a discount to increase yield.

What difference does monolithic vs. modular really make? If Intel has a core on their 28 core die that is defective, they just disable it and sell a 27 core chip. Perhaps it's easier for AMD to find 4 8 core chips with no defects than for Intel to find a 28 core chip with no defects, but Intel can just make a 34 core die sold as a 32 core chip with better yields than AMD's 8 core dies.

Doesnt this just suggest they are leaving some performance on the table then? The reason the Intel processors scale non-linearly is because they run each core faster when there are less cores under load.

Current AMD chiplets come with a maximum of 8 cores.

Yes, they don't disable 1 core out of spite, it is because of the difficulty/cost of a high yield

The situation is even worse for graphics cards


As I stated in my comment: this is true at the beginning of a process node with a new design. But yields improve, and eventually you end up with too many parts in the high bins and nowhere near enough in the value bins-- so you end up blowing fuses on parts that test fully OK to make them be 4 cores or 6 cores.

(And now, Intel is about to let Xeon customers pay to unlock additional cores...)

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