One of the most interesting parts I found was it's not created from a spec, but from scanning and etching an actual chip, useful work for all the chips without complete documentation.
They work on their collection of processes to produce these things, as to basically have non-proprietary way to produce chips from scratch. The other thing I know is that the guy at least has been involved in other layers of production, namely generation and validation of circuitry.
The website I posted links a few pdfs for more info.
I've heard people have decapped these and even recreated (in some fashion) versions of the masks, or circuit layouts. I'd love to figure out how to start a project making actual chips.
Where is the _actual_ explanation of how the chip works? I assume it's been dissected to bits, and that's way more interesting than just "it's been found on lots of boards". What does it actually contain that apparently lets it do things that apparently no one else has managed to achieve at that scale?
I wonder if you could fuzz a chip directly, without having the schematics, so that if the manufacturer inserts something off-the-books it still gets explored.
That is exceptionally cool. They have taken existing best practices in semiconductor fabs and migrated them to an interesting place.
What is missing of course is what their feature sizes are and the part at the end where you cut the die and package it. It is those things that would define the set of things you could put on a single chip.
If you know of any chips taped-out, and shipping in volume, that used any of these as their primary tool, I’d be very interested to know more about that.
I’m aware of chisel used to verify some RISC-V cores that were fabricated, but that’s a research POC, not a volume/production ASIC.
It is pretty cool technique. There are a few things you can do via FIBs but what I'm thinking of here involves cutting a very fine hole through carefully targeted areas of the chip to expose the element in question (or its wires) so we can observe them. We actually have had to do this for debugging a couple of times on 32nm chips (cutting down in and pico probing ). we mostly only got away with it because we had all the floor plans, masks, RTL, documentation and very fancy equipment though, it would have been very difficult otherwise.
Well what I was wondering was, what did they examine to be exact? Did they decap chips and reverse engineer them?
The article as you say, is really short. Too short, there isn't really any information in it, besides "Trend micro said this, take their word for it"...
I've seen a few things on chips that don't make sense, such as wires to nowhere. Then I figured out that these were bug fixes where they had cut connections.
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