One of the most interesting parts I found was it's not created from a spec, but from scanning and etching an actual chip, useful work for all the chips without complete documentation.
That is exceptionally cool. They have taken existing best practices in semiconductor fabs and migrated them to an interesting place.
What is missing of course is what their feature sizes are and the part at the end where you cut the die and package it. It is those things that would define the set of things you could put on a single chip.
What kind of chip layout/validation tools and methods would have been used for this chip? The layout does not appear to be as dense or uniform as other chip images that I've seen. Is the large spacing between elements more indicative of a prototype that would have been refined later in production?
It's manufactured pretty much the same as any other chip, using photolithography. Most of the analog components would be CMOS transistors, just larger. They might use a BiCMOS process with a few extra steps to make bipolar transistors. And there might be an extra step for the capacitors. But overall, the chip uses an old, simple manufacturing process, much easier than cutting-edge processors.
It is an interesting technology. It is basically a packaging innovation, sounds pretty boring I guess, but larger chips have a super-linearly bad effect on yield, so breaking up the design into chiplets is very nice.
I wonder if anyone knows of a good place to look up Intel vs TSMC yield numbers or defect density?
Do you have any good suggested reading material on how to look at chips in the way that you mean? I have no knowledge when it comes to this type of hardware.
Where is the _actual_ explanation of how the chip works? I assume it's been dissected to bits, and that's way more interesting than just "it's been found on lots of boards". What does it actually contain that apparently lets it do things that apparently no one else has managed to achieve at that scale?
It takes a while. I got the chip on Nov 1 and have been working on it since then. (Although it's not the only thing I've been doing.) The process is a combination of taking die photos, tracing out circuitry, understanding the circuits, doing background research, and figuring out how to explain the chip in blog posts.
Based on the captions in the original story, I think it's just a photo of a random signal conditioning coupler, which the chip in question was said to strongly resemble.
It is using a relatively old manufacturing process. It may be small but it is because modern chips are small, not because this is a feat of engineering where they've achieved incredible compute densities.
That's true, I guess my designs are rather more basic than that. I never managed to figure out how to work with these slightly more complicated chips, though I'd like to.
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