That’s an impressive piece of work. I would love to know how far this is from the information in the actual internal documentation. It’s very nice to have some excitement about a mainstream CPU architecture again.
Someone should tell the author about the great lshw, it lists full details of the system board (and everything else) without having to go to a GUI display.
People posting those CPU and SSD screens shots rather than, say, some linked data that contributes to make a graph to forums has such a deleterious effect on people's ability to reason. I suppose eventually we'll end up screen scraping the screen shots.
Thanks. I just found out there's a text abstract one can click to expand ... Snippets:
[...] The cores are our own design; simple 3-address RISCs with read- & write-barriers to support GC, hardware transactional memory, zero-cost high-rez profiling, and some more modest Java-specific tweaks. [...] history with designing our own chips (1st silicon back from the fab had problems like the bits in the odd-numbered registers bleeding into the even-numbered registers)[...]
Pretty cool stuff. I built a dumber version of this a few years ago that just did differential fuzzing between actual cores from different vendors, but without feedback on microarchitectural state it didn't get very far. Good to see people demonstrating how public descriptions of your parts yield concrete security benefits.
Thanks! I did miss that page. But even though they mention "... calls for the development of software tools to help programming the new architecture...", I'm still unsure as to how programming for such a processor might look like.
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