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Its not just the engineers leaving, the newer chips will also be produced on n4 instead of n3.


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I expect AMD to start using N3 after Apple and Intel have moved on to N2 (or maybe 20A in Intel's case) in 2024 so there's less competition for wafers.

The lede is buried here a bit. N4 is an optimization of N5, so you'd expect that foundry to support N4.

The commitment to additionally making an N3 line, and for it to make a significant amount of wafers for customers other than the DoD is big news.


Maybe they skipped 7nm and are going straight to 5nm for RDNA2 in CPUs. Zen4 based mobile chips will probably be a very interesting release.

They were struggling with Intel 10 (14nm). That led to the change in the leadership. Are they struggling with Intel 7, 4? Or future Intel 3, 20A, 18A?

From what I have read, 4nm is not really a significant process change and is really just a variant of 5nm. There have been only minimal improvements in chips going form 5nm to 4nm as a result. 3nm really is different.

Word on the street is also that the 14nm death march resulted in a lot of engineers taking early retirement which left them in a worse position to pursue 10nm.

I recognize that, but I'm assuming there was an assumption 7nm was coming up soon. As that is no longer the case, would they change their plans?

Well, 3nm is 2022, so the newer M variant in this article wont be using it.

That is because N3E was suppose to be on GAAFET and they had to push it back to N2 while reworking on N3E. You will get some SRAM scaling again on N2 and 14A.

I would guess that was in part driven by Intel announcing the delay of 7nm products to 2023.

They'll probably shift to 6nm (7nm++, basically) next.

That whole thing is temporary until 2021 when other companies will get a chance to use 5nm fabs.

HiSilicon also made 5nm chip but it's gone.

> Auto manufacturers need 380nm production lines.

I think you mean 350nm.

This isn't surprising; a lot of nifty features got axed after 350nm, like having two full-fledged polysilicon layers (a few subsequent processes technically have two poly layers but one of them is totally crippled and can only be used for flash cells).


Don't get used to it. N3E has no SRAM density improvement over N5 and its TSMC's "real" N3 node since N3B (Base) is prohibitively expensive for all but the very richest customers. N3B is such an economic dead end of a node that TSMC doesn't even have an upgrade path to transition N3B designs to N3E.

Wait, did I read this right - Intel is going to be the last one to get 10nm?

> Samsung, for one, plans to ship its 10nm finFET technology by year’s end.

> TSMC will move into 10nm production in early 2017

> Intel will move into 10nm production by mid-2017


TSMC is phasing out 180nm officially already for 2 years due to demand on more advanced nodes like 65nm or 40nm. All the BCD stuff is implemented on those processes too. They are moving the equipment used in 180nm to these newer nodes. I think they don't want anything laeger than 110nm.

From what I heard, Intel 14nm was running a little late and management pushed the engineering team really hard.

As a result a bunch of the greybeards left, so for 10nm a bunch of institutional knowledge was completely missing and they had to learn everything again the hard way.


Not only that, by the time they figure how to do it the rest of the world will have moved on by at least 2 generations. SMIC has announced 14nm (but shipments in volume aren't clear), TSMC will have 5nm chips shipping in volume by the end of the month.
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