N4 is still (despite the name) part of TSMC’s 5nm process family and offers little to no performance/efficiency improvement over N5P.
N4 increases the number of EUV layers so the main improvements should be in cost and yield which would have been interesting to Apple, but N5P hit volume manufacturing earlier allowing Apple to ship the M2 earlier and with more capacity.
Waiting for N3 would have offered a considerable performance and efficiency boost but that’d realistically have delayed M2 to the first half of 2023.
As someone else mentioned in the other thread, it's a bit odd that they're aiming for 5nm production at this fab in 2024 because 3nm should be ready to go by then. You'd sorta think that since they're already breaking ground on their 3nm fab in Taiwan that any other new builds would be 3nm as well.
From what I have read, 4nm is not really a significant process change and is really just a variant of 5nm. There have been only minimal improvements in chips going form 5nm to 4nm as a result. 3nm really is different.
N7 is a rough node to target. You have the high capital costs for NRE being an EUV node, but N5 is supposed to be cheaper to manufacturer chips on pretty much as soon as N3 is in full swing.
So those companies would probably be targeting something in the range of 14nm to 10nm in order to take advantage of the fire sale on late DUV tooling to prove that they can make a working chip to investors, and then leapfrog to N5 after the giants have jumped to N3.
I expect AMD to start using N3 after Apple and Intel have moved on to N2 (or maybe 20A in Intel's case) in 2024 so there's less competition for wafers.
It's only the press clinging onto this - TSMC themselves refer to it as N3B, N3E, N6/N7 etc, Intel's process is 10ESF or Intel 7, all without putting the "nm" there.
It's still useful to roughly group different foundry processes, but nobody who is actually paying the $100mm++ to use these processes is relying solely on rough grouping.
Did I miss the news that they have a new 3nm process working, even badly? Or have they just defined a variation on their 4nm process and are calling it 3nm?
Most vendors can do 3nm, but probably not at production scale other than ASML.
28nm is very worrying from a NatSec standpoint though - way more than leading edge nodes - as that enough to produce a Sandy Bridge or Maxwell type architecture, which meets the needs for most American defense applications (eg. drones, precision missiles, C-RAM, etc)
Russia manufactures their Elbrus-8s architecture using 28nm lithography as well, and that's the backbone for most of their newer precision, electronics, and avionics weapons systems.
Nice to see another confirmation that N3 is expected to be in high volume production by the end of the year, even if delivery to customers is still pushed out until early next year.
>TSMC's first 3 nm-class node is called N3 and this one is on track to start high volume manufacturing (HVM) in the second half of this year. Actual chips are set to be delivered to customers in early 2023.
Without owning the foundry, it's not clear if this is an IBM tech demo that goes nowhere, or if it effects GF's roadmap. GF uses a Samsung process for 14nm (really 14/20 hybrid), so it really looks like IBM is out of the foundry business as far as taking a process all the way to manufacturing.
GF might leapfrog down to 7nm, but if they aren't even fully 14nm at this point, does that really seem plausible?
Providing a little more context before things get blow out of proportion.
This is the first time TSMC has done two large feature set in one node generation. TSMC's N2 will first use gate-all-around (GAA), with an improved N2P coming with BackSide Power Delivery Network (BSPDN).
As with any new large node features, capacity will be constrained, so instead of the usual one additional Fab online per year expansion in leading node, they are bringing online 3 in the space of 2 years. This is also discounting that we dont know the total Wafer output of each Fab. But if we look at the recent Q4 report it does seems HPC ( or likely AI ) has infinite appetite for wafer capacity. So I wont be surprised if it is indeed a substantial increase in wafer capacity on leading node.
We will know ( or we can infer it ) once they start doing 2nm revenue reporting. TSMC tends to be very transparent with these sort of things. Something I hope Intel IFS will copy as well.
The commitment to additionally making an N3 line, and for it to make a significant amount of wafers for customers other than the DoD is big news.
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