- Octavo Systems puts Ti SOC's and PMIC's in a package with outside vendor DRAM and ROM chips. - NXP builds some auto parts with a mix of NXP chips on different process nodes and third party flash.

I spent a few years designing these types of systems. In my mind the the biggest value of a standard like this is to push companies to make it worth their while to sell "known-good-die" (KGD) or fully-tested die.

Modern chip manufacturing basically has a two part test flow - a partial test of each die on the wafer then after slicing and packaging each part goes through final test. Packaging is expensive and so imagine building a multi chip module which might have an SOC, DRAM, PMIC and FLASH bare dies and then it goes through final test and each of those dies had a 90% final test yield then the MCM might only have a 65% yield. That's a lot of money down the drain.....

If I built the same part using fully tested die then my yields should be closer to 95-99% - basically the failures are not due to bad silicon, but bad packaging....

Right now it's tough to get companies to spend the resources on a KGD test program because the market is just too small/scattered. A standard helps to build a market.

With that said - I haven't seen this standard yet. I just requested a copy. From the little info available on the website (https://www.uciexpress.org/) it sounds like it's just an IO interconnect standard - along the lines of something like MIPI DSI + D-PHY. That's a good start but the dream of "lego" like chips will require standardized foot prints and pinouts which may just never be feasible but there are people exploring this idea....

True, the very advanced packaging techniques, such as TSMC CoWoS or Intel EMIB, are done at the fabs by those companies. These packages are for very high performance multi-chip interconnects. In both cases, the "package" itself actually is partially constructed from silicon, so we are kind of blurring the lines between what is "chip" and what is "package". The vast majority of chips do not use packages anywhere near this advanced and are not done at fabs.

Also, it's not crazy to ship finished wafers (i.e. "unpackaged die"); it's standard practice. Once the final process steps are complete in the fab, the chip is not as sensitive to fine particles any more. The wafers get loaded into cassettes then vacuum-sealed in anti-static bags. They ship out to the backend assembly sites just fine. In fact, globally, there are probably ~100,000 wafers shipped like this every day.

> Intel sells lots of CPUs that aren't soldered to PCBs.

True. But if you are buying an LGA socketed Intel CPU, the silicon die had to first be mounted on a substrate and the heatspreader attached. That wasn't done at fab, it was done at backend assembly. Ever notice that Intel CPU's often say something about "assembled in Malaysia" on top? That's because it was assembled in Malaysia. Intel does not have any semiconductor fabs in Malaysia, meaning, they fabbed it in one place and assembled it in another.

If you are a company like Dell or HP and you are buying the laptop BGA CPUs, Intel still had to assemble those into the BGA package before shipping to Dell/HP. And the BGA package assembly also is not done at fab.

They would be manufacturing 4x Max dies, which have no yield issues, and then combine them together in a separate process.

I wonder if anyone knows of a good place to look up Intel vs TSMC yield numbers or defect density?

This part isn't new, or why this is significant. For example, AMD has been doing this since Zen 2 (Ryzen 2xxx), combining 14nm and 7nm components.

On the other hand, the top chip designers and foundries working together and standardizing is potentially very significant, though I reserve judgement until actual products are produced on this new standard.

Assuming the company follows normal manufacturing processes (and assuming that company is "fabless" then this is a pretty safe assumption) then there is no risk of mixing different silicon from different vendors/fabs in a single package. This is being done today. Currently designers do have to take into account mixing parts that were designed for various package technologies. If a chip was designed for "flip-chp" and another chip for "wire-bond" then putting them both in the same package might require some different packaging techniques...

That said - I'd assume if a company was going to build a chip and specifically market it for this new UCIe standard then they'd probably target a WLCSP type final process which is fairly common today.

https://amkor.com/packaging/wafer-level-packaging/wlcsp/

I'm interested in advanced packaging. Does anyone know anything about it? My impression is that BGA, MicroBGA, CSP, WLP, Flip-Chip are the evolutionary dead end of packaging, you can't really find a denser way to put a chip on the board. So instead, you put more things into the package or onto the interposer, and for the user, the new "module" can be used just like a chip, this is the System-in-Package approach, such as integrating the chiplet and RAM to a processor, or stacking multiple silicon dies on top of each other. This is my understanding, but is there anything new to see?

[0] https://news.ycombinator.com/item?id=37432948

[Packaging separate dies, each made on distinct process] is cheaper than [use 1 process that is sub-optimal for big part(s) of the chip].

Or: advanced IC packaging is cheaper than advanced semiconductor manufacturing.

Still surprising this works for a <$1 chip. But makes sense considering what a new semiconductor fab costs nowadays.