I am impressed by the fabrication technology for these heterogenous systems. It was already complex enough to fabricate a CPU, but chiplets require incredible precision for placing the die on the interposer wafer for soldering. And the coplanarity of the whole assembly is critical, else it will be impossible to effectively cool. It's incredible that any of it works.
Needing to manufacture and assemble several components in this fashion must be awful for yields. I'd imagine AMDs chiplet process is much more forgiving.
Oh no, the packaging connections are (guessing) thousands of nanometres. Much easier to build, much cheaper. Also, the process of moving to multi-chip packages means the process yield for the chiplets is much higher. It's a bloody good idea :)
Indistinguishable From Magic: Manufacturing Modern Computer Chips [0]. This talk is delivered really well and always leaves me with a sense of awe in how CRAZY it is that humans figured out integrated circuits. Its a bit out of date, but it gives enough of a peek under the hood to understand why Intel has had such difficulties going to 10 and 7mn processes[1].
That is exceptionally cool. They have taken existing best practices in semiconductor fabs and migrated them to an interesting place.
What is missing of course is what their feature sizes are and the part at the end where you cut the die and package it. It is those things that would define the set of things you could put on a single chip.
It is an interesting technology. It is basically a packaging innovation, sounds pretty boring I guess, but larger chips have a super-linearly bad effect on yield, so breaking up the design into chiplets is very nice.
I wonder if anyone knows of a good place to look up Intel vs TSMC yield numbers or defect density?
If you haven't watched it, there was a fantastic 2009 talk (given during HOPE09) on what goes into fabrication called "Indistinguishable From Magic: Manufacturing Modern Computer Chips" [1]. Keeping in mind things have advanced even farther over the subsequent decade, even at that point it was mind blowing what goes into the hardware at the core of what we all do. The level of purity and consistency needed for a lot of basic inputs is measured in atoms, really digging into the details it's amazing some of this works at all let alone with high yields. Helps give some context of how an incident like this can happen and how easily the cost could rapidly rise to eye watering levels.
I think Andor has posted on HN since too with some other high level talk, though not further updates per se since unsurprisingly details around fabrications are very heavily guarded trade secrets. I still rewatch it every year or two, it remains a real source of wonder to me what we've pulled off there.
I'm surprised this hasn't been done before; a monolithic wafer can achieve denser interconnects, and is arguably simpler than a multi-chip module.
On the other hand, multi-chip modules can combine the working chips in low-yield wafers, whereas a monolithic wafer would likely contain many failed blocks, uselessly taking up space / distancing the working chips.
Cooling isn't really a problem, as the TDP scales with area as in other chips. Water cooling or heat pipes can transport the heat away to a large heat sink. 3D / die-stacked chips have a harder cooling problem, potentially requiring something like an intra-chip circulatory system.
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